The present invention relates to a method for modulating a pulse width, employed to control such a power converter apparatus as an inverter apparatus that drives an AC motor at a variable speed, as well as a power converter apparatus or an inverter apparatus that employs the method. More particularly, the present invention relates to a method for modulating a pulse width so as to be preferable to detect an AC output current from an output of a DC current detector, as well as a power converter apparatus that employs the method.
Generally, each of power converter apparatus used to drive an AC motor at a variable speed respectively reduces the higher harmonics by modulating the pulse width of the output waveform. FIG. 10 shows the power converter apparatus 10 having an inverter unit that uses a conventional pulse width modulation method. In the power converter apparatus 10, a voltage supplied from such an AC power source as a commercial three-phase AC power source is rectified in a rectification circuit 2, then converted to a DC voltage. The DC voltage is then smoothed in a smoothing capacitor 3 so as to obtain a smoothed DC voltage. This smoothed DC voltage is switched by switching elements Qu, Qv, Qw, Qx, Qy, and Qz in the inverter so as to supply a variable voltage and variable frequency AC power to a motor 4. A diode is connected in reverse parallel with the switching elements Qu, Qv, Qw, Qx, Qy, and Qz so as to flow an opposite direction current therein.
A current detector 5 detects a DC current Idc while a current detector 7 detects a U-phase motor current Iu, a V-phase motor current Iv, and a W-phase motor current Iw that flow in the motor 4 based on the detected DC current Idc and gate signals Gu, Gv, Gw, Gx, Gy, and Gz output from a PWM controller 6. The official gazette of Japanese Patent laid-Open No. 6-153526 discloses in detail a method for detecting three-phase AC currents Iu, Iv, and Iw from this DC current Idc by calculating.
A motor controller 8 outputs a U-phase AC voltage command Eu, a V-phase AC voltage command Ev, and a W-phase AC voltage command Ew according to the detected motor currents Iu, Iv, and Iw, as well as a speed command Fr* received from external. The PWM (Pulse Width Modulation) controller 6 outputs the gate signals Gu, Gv, Gw, Gx, Gy, and Gz used to instruct each of the switching elements Qu, Qv, Qw, Qx, Qy, and Qz to make switching according to the AC voltage commands Eu, Ev, and Ew.
FIG. 11 shows a block diagram of the PWM controller 6. A carrier wave generator 601 outputs a carrier wave C (refer to the waveform C shown in FIG. 12), which is a triangle wave of a frequency Fc according to a carrier wave frequency command Fc set by a carrier wave frequency setting device 608. A U-phase comparator 602 that outputs a gate signal Gu compares the U-phase AC voltage command Eu with the carrier wave C to output a H-level (High level) signal when the U-phase AC voltage command Eu is large and a L-level (Low level) signal when the Eu is small in value respectively. An inverter 605 that outputs a gate signal Gx outputs an H-level signal when the gate signal Gu is on the L-level, and outputs an L-level signal when the Gu is on the L-level. Other gate signals Gv, Gy, Gw, and Gz can also be obtained similarly by comparing each of the AC voltage commands Ev and Ew with the carrier wave C.
FIG. 12 shows the waveforms of such components as the PWM controller 6; the horizontal axis denotes the time. In FIG. 12, Eu, Ev, and Ew denote AC voltage commands (phase voltage commands) and C denotes a carrier wave used to modulate the pulse width of each of those AC voltage commands. Gu, Gv, and Gw denote U, V, and W phase gate signals obtained by comparing each of the phase AC voltage commands Eu, Ev, and Ew with the carrier C and setting the signal on the H level when the Eu/Ev/Ew is larger than C and set on the L level when the command is smaller than C in value respectively. When the gate signals Gu, Gv, and Gw are set on the H level, the corresponding switching elements Qu, Qv, and Qw are turned on and the corresponding switching elements Qx, Qy, and Qz are turned off. On the other hand, when the gate signals Gu, Gv, and Gw are set on the L level, the corresponding switching elements Qu, Qv, and Qw are turned off and the corresponding switching elements Qx, Qy, and Qz are turned on. A symbol Vuv denotes a line-to-line voltage between U and V phases. Iu, Iv, and Iw are output currents of the inverter unit. Idc denotes a DC current.
FIG. 13 shows details of a period T1 shown in FIG. 12. The horizontal axis of each waveform denotes the time and the vertical axis denotes, from top to bottom, the gate signals Gu, Gv, and Gw, as well as the line-to-line voltage Vuv, the line-to-line voltage Vvw between V and W phase outputs, the line-to-line voltage Vwu between W and V phase outputs, and the DC current Idc. The current detector 7 detects the motor currents Iu, Iv, and Iw from the DC current Idc with use of the gate signals. The description of the details of this detecting method will be omitted here, since it is described in detail in the official gazette of Japanese patent Laid-Open No. 6-153526.
As described in the official gazette of Japanese Patent Laid-Open No. 6-153526, the gate signals Gu, Gv, and Gw can be represented by binary codes; eight combinations of those codes are possible. Concretely, the combinations are V0=(1,1,1), V1=(0,1,1), V2=(1,0,1), V3=(0,0,1), V4=(1,1,0), V5=(0,1,0), V6=(1,0,0), and V7=(0,0,0). The one phase is set on the H level in V3, V5, and V6 while two phases are set on the H level in V1, V2, and V4.
However, when the U-phase AC voltage command Eu, the V-phase AC voltage command Ev, and the W-phase AC voltage command Ew are small in amplitude, the periods Tb, Tc, Te, and Tf in which the DC current Idc flows respectively become short. Although the Idc rises instantly in FIG. 13, since its waveform is an ideal one, the Idc actually includes a delay time in its rising. In some cases, an overshoot occurs in the Idc. Consequently, when the Idc flowing period is short, accurate sampling of current values comes to be difficult.
Furthermore, as disclosed in the official gazette of Japanese Patent Laid-Open No. 9-56177, a dead time (or non-lap period) is set between gate patterns so as to prevent the upper/lower arm of the inverter from being short-circuited to be caused by a delay in the operation of a switching element.
FIGS. 14 through 16 show examples in which such a dead time period is set respectively. In FIG. 14, a section, which is concretely a period A, includes two dead time periods Txcex4. In the period A ranged from an intersection point between the W-phase voltage command value and the carrier wave waveform to another intersection point between the U-phase voltage command value and the carrier wave waveform, the gate patterns V4 and V6 that can detect a current in the DC part respectively continue. FIG. 15 shows timings of the gate signals when a small value is set for each of the phase commands shown in FIG. 14. Generally, a dead time period Txcex4 is set for a certain time. Although the period A becomes short, the dead time period T xcex4 exists with the certain time. Consequently, no current can be detected in the period A when the period A becomes shorter than the two dead time periods 2Txcex4. FIG. 16 shows the timings of the gate signals when the carrier wave frequency is raised to make the carrier cycle short as shown in FIG. 14. Also in this connection, while the period A is set shortly, the Txcex4 is kept constant. Current detection is disabled when the period A becomes shorter than 2Txcex4.
Such way, the current sampling period becomes short, thereby current sampling is difficult due to the delay of the actual current in its rising, occurrence of the overshoot of the DC current Idc, the presence of a dead time period, etc.
This is why the carrier wave frequency must be lowered to secure a sampling period enough. When the carrier frequency is lowered, however, a problem rises; the magnetic noise from the motor and/or load increases as disclosed in the official gazettes of Japanese Patent Laid-Open No. 61-105047 and No. 53-50422. The official gazette of Japanese Patent Laid-Open No. 61-105047 thus recommends that the carrier wave frequency should be set at 8 kHz to 16 kHz so as to reduce the magnetic noise.
It is an object of the present invention to solve the above conventional problems, thereby providing a method for modulating a pulse width so as to secure a sampling time enough to detect a current, as well as a power converter apparatus or an inverter apparatus that employs the method.
It is an another object of the present invention to suppress magnetic noise of induction motor which is a load of the power converter apparatus or the inverter apparatus that employs the method.
In an aspect of the invention, a pulse width modulation (PWM) method modulates the pulse width based on a modulated wave and a carrier wave and supplies gate signals to a power converter, and detects each phase AC current of the power converter based on a detected DC current and the gate signals, wherein the PWM method inserts the carrier wave with a long carrier cycle longer than the preset carrier cycle periodically, and samples the detected DC current during the long carrier cycle.
In an another aspect of the invention, when the AC voltage of said power converter is under a predetermined value, a pulse width modulation (PWM) method inserts only one cycle of the carrier wave with the long carrier cycle of an integer multiple of the preset carrier cycle every once at 1 ms or over.
In an another aspect of the invention, a pulse width modulation (PWM) method inserts the carrier wave with the long carrier cycle within a range of xcfx80/6 rad around the maximum value of the line-to-line voltage of the AC periodically.